ESTONIAN ACADEMY
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eesti teaduste
akadeemia kirjastus
PUBLISHED
SINCE 1952
 
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proceedings
of the estonian academy of sciences
ISSN 1736-7530 (Electronic)
ISSN 1736-6046 (Print)
Impact Factor (2020): 1.045

Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems; pp. 323–335

Full article in PDF format | https://doi.org/10.3176/proc.2017.3.07

Authors
Valery Sklyarov, Iouliia Skliarova, Artjom Rjabov, Alexander Sudnitson

Abstract

The paper suggests and describes two architectures for parallel data sort. The first architecture is applicable to large data sets and it combines three stages of data processing: data sorting in hardware (in a Field-Programmable Gate Arrays – FPGA), merging preliminary sorted blocks in hardware (in the FPGA), and merging large subsets received from the FPGA in general-purpose software. Dataexchange between the FPGA anda general-purpose computeris organized throughafast Peripheral Component Interconnect (PCI) expressbus.The second architectureis applicabletosmalldatasetsandit enablessortingtobedoneatthetimeofdata acquisition,i.e.as soon as the last data item is received, the sorted items can be transferred immediately. The results of experiments clearly demonstrate the advantages of the proposed architectures that permit the reduction of the required hardware resources and increasing throughput compared to the results reported in publications and software functions targeted to data sorting.


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