ESTONIAN ACADEMY
PUBLISHERS
eesti teaduste
akadeemia kirjastus
PUBLISHED
SINCE 1952
 
Proceeding cover
proceedings
of the estonian academy of sciences
ISSN 1736-7530 (Electronic)
ISSN 1736-6046 (Print)
Impact Factor (2020): 1.045

Environment for the analysis of functional self-test quality in digital systems; pp. 151–162

Full article in PDF format | doi: 10.3176/proc.2014.2.05

Authors
Raimund Ubar, Sergei Kostin, Helena Kruus, Margit Aarna, Sergei Devadze

Abstract

Dependability of computer architectures has become one of the most important engineering concerns. One of the possibilities to increase the dependability is to develop architectures with dedicated self-test capabilities which allow achieving high quality of testing in terms of fault coverage. We propose a new methodology for Built-in Self-Test (BIST), which combines the inherent functionality of the architecture with a small amount of pre-generated test data stored in the memory, and uses for monitoring of the test process a restricted number of test points, configured as a set of signature analysers. Contrary to the traditional scan-path based logic BIST, the proposed solution does not need additional hardware for test pattern generation, and will not have any impact on the working performance of the system. On the other hand, testing at normal working conditions allows exercising the system on-line and at-speed, facilitating the detection of dynamic faults like delays and crosstalks to achieve high test quality. The new self-test method is free from the negative aspect of over-testing, compared to the traditional logic BIST approaches. A method is presented to generate optimized test data for selected test routines, and to choose minimum set of test-points for response analysis. A tool framework is proposed to emulate self-testing architectures, and to carry out fault simulation for evaluating the test quality in terms of fault coverage.


References

  1. Bernardi, P., Grosso, M., Sanchez, E., and Sonza Reorda, M. Software-based self-test of embedded micro­processors. In Design and Test Technology for Dependable Systems-on-Chip (Ubar, R., Raik, J., and Vierhaus, T., eds). Information Science Reference, Igi Global, Herschey, New York, 2011, 338–359.

  2. Mak, T. M., Krstic, A., Cheng, K.-T., and Wang, Li.-C. New challenges in delay testing of nanometer, multi-gigahertz designs. IEEE Des. Test Comput., 2004, 21, 241–248.
http://dx.doi.org/10.1109/MDT.2004.42

  3. Bushard, L., Chelstrom, N., Ferguson, S., and Keller, B. DFT of the cell processor and its impact on EDA test software. In Proc. IEEE Asian Test Symposium. Fukuoka, 2006, 369–374.

  4. Wang, S. and Gupta, S. K. ATPG for heat dissipation minimization during scan testing. In Proc. ACM IEEE Design Automation Conference. Anaheim, 1997, 614–619.
http://dx.doi.org/10.1109/DAC.1997.597219

  5. Chen, L., Ravi, S., Raghunathan, A., and Dey, S. A scal­able software-based self-test methodology for pro­gramm­able processors. In Proc. IEEE/ACM Design Automation Conference. Anaheim, 2003, 548–553.

  6. Wang, L.-T., Wu, C.-W., and Wen, X. VLSI Test Principles and Architectures. Morgan Kaufmann, San Francisco, 2006.

  7. Gizopoulos, D. Advances in Electronic Testing: Challenges and Methodologies. Springer, 2006.

  8. Hetherington, G., Fryars, T., Tamarapalli, N., Kassab, M., Hassan, A., and Rajski, J. Logic BIST for large industrial designs. In Proc. IEEE International Test Conference. Atlantic City, 1999, 358–367.

  9. Hortensius, P. D., McLeod, R. D., and Podaima, B. W. Cellular automata circuits for BIST. IBM J. Res. Dev., 1990, 34, 389–405.
http://dx.doi.org/10.1147/rd.342.0389

10. Eichelberger, E. B. and Lindbloom, E. Random pattern coverage enhancement and diagnosis for LSSD logic self-test. IBM J. Res. Dev., 1983, 27, 265–272.
http://dx.doi.org/10.1147/rd.273.0265

11. Tamarapalli, N. and Rajski, J. Constructive multi-phase test point insertion for scan-based BIST. In Proc. IEEE International Test Conference. Washington, DC, 1996, 649–658.

12. Touba, N. A. and McCluskey, E. J. Test point insertion based on path tracing. In Proc. 14th IEEE VLSI Test Symposium. Princeton, 1996, 2–8.
http://dx.doi.org/10.1109/VTEST.1996.510828

13. Yang, J.-S., Nadeau-Dostie, B., and Touba, N. Reducing test point area for BIST through greater use of functional flip-flops to drive control points. In Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems. Chicago, 2009, 20–28.

14. Koenemann, B. LFSR-coded test patterns for scan designs. In Proc. European Test Conference. Munich, 1991, 237–242.

15. Zhao, Z., Pouya, B., and Touba, N. A. BETSY: synthesiz­ing circuits for a specified BIST environment. In Proc. IEEE International Test Conference. Washington, 1998, 144–153.

16. Agrawal, V. K. and Cerny, E. Store and generate built-in test approach. In Proc. Fault-Tolerant Computing Symposium. Portland, Maine, 1981, 35–40.

17. Wunderlich, H.-J. and Kiefer, G. Bit flipping BIST. In Proc. IEEE ACM International Conference on Com­puter-Aided Design. San Jose, CA, 1996, 337–343.
http://dx.doi.org/10.1109/ICCAD.1996.569803

18. Touba, N. A. and McCluskey, E. J. Bit-fixing in pseudo­random sequences for scan BIST. IEEE Trans. CAD Integr. Circ. Syst., 2001, 20, 545–555.
http://dx.doi.org/10.1109/43.918212

19. Hellebrand, S., Tarnick, S., Rajski, J., and Courtois, B. Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers. In Proc. IEEE International Test Conference. Baltimore, MD, 1992, 120–129.

20. Touba, N. A. and McCluskey, E. J. Transformed pseudo-random patterns for BIST. In Proc. VLSI Test Symposium. Princeton, NJ, 1995, 410–416.

21. Dorsch, R. and Wunderlich, H.-J. Accumulator based deterministic BIST. In Proc. IEEE International Test Conference. Washington, DC, 1998, 412–421.

22. Rajski, J. and Tyszer, J. Arithmetic BIST in Embedded Systems. Prentice-Hall, NJ, 1998, 268.

23. Hellebrand, S., Wunderlich, H.-J., and Hertwig, A. Mixed-mode BIST using embedded processors. J. Electron. Test. (JETTA), 1998, 12, 127–138.
http://dx.doi.org/10.1023/A:1008294125692

24. Voyiatzis, I., Gizopoulos, D., and Paschalis, A. Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time. IEEE Trans. VLSI Syst., 2005, 13, 1079–1086.
http://dx.doi.org/10.1109/TVLSI.2005.857159

25. Knuth, D. E. The Art of Computer Programming. Vol. 2. Addison-Wesley, Reading, Massachusetts, 1981.

26. Rajski, J. and Tyszer, J. Accumulator-based compaction of test responses. IEEE Trans. Comput., 1993, 42, 643–650.
http://dx.doi.org/10.1109/12.277285

27. Gizopoulos, D., Psarakis, M., Hatzimihail, M., and Maniatakos, M. Systematic software-based self-test for pipelined processors. IEEE Trans. VLSI Syst., 2008, 16, 1441–1453.
http://dx.doi.org/10.1109/TVLSI.2008.2000866

28. Chen, L. and Dey, S. DEFUSE: A deterministic functional self-test methodology for processors. In Proc. VLSI Test Symposium. Montreal, 2000, 255–262.

29. Jayaraman, K., Vedula, V. M., and Abraham, J. A. Native mode functional self-test generation for systems-on-chip. In Proc. International Symposium on Quality Electronic Design. San Jose, CA, 2002, 280–285.
http://dx.doi.org/10.1109/ISQED.2002.996752

30. Apostolakis, A., Psarakis, M., Gizopoulos, D., and Paschalis, A. A functional self-test approach for peripheral cores in processor-based SoCs. In Proc. International On-Line Testing Symposium. Crete, 2007, 271–276.

31. Koal, T., Kothe, R., and Vierhaus, H. T. SoC self test based on a test-processor. In Design and Test Techno­logy for Dependable Systems-on-Chip (Ubar, R., Raik, J., and Vierhaus, T., eds). IGI Global, Herschey, New York, 2011, 360–376.

32. Ubar, R., Devadze, S., Raik, J., and Jutman, A. Parallel X-fault simulation with critical path tracing technique. In Proc. IEEE Conference on Design, Automation & Test in Europe. Dresden, 2010, 879–884.

33. Java Genetic Algorithms Package. http://jgap.sourceforge.net (accessed 18.02.2014).

34. Brglez, F. and Fujiwara, H. A neutral netlist of 10 com­bina­tional benchmark circuits and a target translator in fortran. In Proc. IEEE International Symposium on Circuits and Systems. Kyoto, 1985, 785–794.

35. Brglez, F., Bryan, D., and Kominski, K. Combinational profiles of sequential benchmark circuits. In Proc. International Symposium on Circuits and Systems. Portland, OR, 1989, 1929–1934.
http://dx.doi.org/10.1109/ISCAS.1989.100747

36. Corno, F., Reorda, M. S., and Squillero, G. RT-level ITC’99 benchmarks and first ATPG results. IEEE Des. Test Comput., 2000, 17, 44–53.
http://dx.doi.org/10.1109/54.867894


Back to Issue