Dependability of computer architectures has become one of the most important engineering concerns. One of the possibilities to increase the dependability is to develop architectures with dedicated self-test capabilities which allow achieving high quality of testing in terms of fault coverage. We propose a new methodology for Built-in Self-Test (BIST), which combines the inherent functionality of the architecture with a small amount of pre-generated test data stored in the memory, and uses for monitoring of the test process a restricted number of test points, configured as a set of signature analysers. Contrary to the traditional scan-path based logic BIST, the proposed solution does not need additional hardware for test pattern generation, and will not have any impact on the working performance of the system. On the other hand, testing at normal working conditions allows exercising the system on-line and at-speed, facilitating the detection of dynamic faults like delays and crosstalks to achieve high test quality. The new self-test method is free from the negative aspect of over-testing, compared to the traditional logic BIST approaches. A method is presented to generate optimized test data for selected test routines, and to choose minimum set of test-points for response analysis. A tool framework is proposed to emulate self-testing architectures, and to carry out fault simulation for evaluating the test quality in terms of fault coverage.
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