CONTENTS &
ABSTRACTS
In English. Summaries in Estonian
Proceedings of the
Estonian Academy of Sciences.
Engineering
Volume 7 No. 4
December 2001
Guest
editorial; 251–252
Mart MIN
Module
level defect simulation in digital circuits; 253–268
Wieslaw KUZMICZ, Witold PLESKACZ, Jaan RAIK, and Raimund UBAR
Abstract. A new method for parametric defect modelling is developed for calculating the conditions for activating physical defects in the modules (for example, in library components) of digital circuits. The method affords for the first time the possibility to handle the defects which increase the number of states in the circuit. By using the concept of functional faults, the new method of defect modelling by logic conditions is generalized for hierarchical fault simulation. A method is proposed to find the types of faults that may occur in a real circuit, to determine their probabilities, and to find the input test patterns that detect these faults. A new hierarchical defect-oriented fault simulation method is presented. At the higher (module) level simulation we use the functional fault model, at the lower level the defect/fault relationships in the form of defect coverage table and conditional defect probabilities. Experimental data of the hierarchical defect-oriented simulation for ISCAS’85 benchmarks are presented, which show that classical stuck-at fault based simulation and the test coverage calculation, based on counting defects without considering defect probabilities, may lead to considerable overestimation of results.
Key words: digital circuits, component libraries, physical defects, faults, stuck-at fault model, functional faults, defect/fault relationships, probabilistic defect analysis, defect-oriented fault simulation.
Application
of structurally synthesized binary decision diagrams for timing simulation of
digital circuits; 269–288
Artur JUTMAN and Raimund UBAR
Abstract. Meeting the timing requirements is an important constraint imposed on highly integrated circuits, and the verification of timing of a circuit before manufacturing is one of the critical tasks to be solved by CAD tools. In this paper, we present a novel technique to speed up gate-level timing simulation that is based on Structurally Synthesized Binary Decision Diagrams (SSBDD), which have already found application as an efficient mathematical model to represent digital circuits. The new approach uses path delays instead of gate delays for tree-like subcircuits (macros). Therefore timing waveforms are calculated not for all internal nodes of the gate-level circuit, but only for outputs of macros. The macros are represented by SSBDDs, which enable a fast computation of delays for macros. We show that the speed-up of timing simulation is directly proportional to the average size of macros in the circuit. The new approach to speed up the timing simulation is supported by encouraging experimental results.
Key words: timing simulation, binary decision diagrams, delay modelling.
Modelling
non-linear systems by extended Fourier series; 289–308
Vello KUKK
Abstract. The paper deals with modelling of non-linear systems consisting of highly oscillating subsystems. Signals are represented as Fourier series extended by half-frequency components that make it possible to model the transients. Macromodels for non-linear transformations are based on harmonic linearization, implemented by the Chebyshev expansion. This enables independent description of the non-linear transformation and calculation of the Chebyshev transformation of waveforms that appear during the solution. Integration method based on this approach has excellent stability properties and its accuracy can be checked by using different number of harmonics.
Key words: modelling, non-linear systems, oscillators, Fourier series, Chebyshev transformation.
On
frequency adaptation in an extended block-adaptive Fourier analyser;
309–330
Ants RONK
Abstract. The aim of this work is to form a basis for developing an efficient adaptive multi-frequency adaptation algorithm for an extended block-adaptive Fourier analyser (EBAFA), which performs simultaneously separation and analysis of its input signal’s periodic components of different frequencies and waveforms. A brief description of EBAFA is given and several possibilities to improve estimation of differences between fundamental frequencies of signal’s periodic components and corresponding resonator groups of EBAFA are considered.
Key words: adaptive filters, observers, resonators, spectral analysis, waveform analysis, frequency estimation.
Linearity
restrictions for a class of phase frequency detectors;
331–346
Vello MÄNNAMA and Toivo PAAVLE
Abstract. In this paper, the transfer characteristic of a class of phase frequency detectors is analysed and modelled for simulations. It is demonstrated that the reasons of non-linearity of the transfer characteristic may originate both from the charge pump and the logic control unit of the phase frequency detector. Restricted slew rate is found to be one of the main reasons of non-linearity of the charge pump, determining the minimum duration of control signals. For a generalized structure of the control unit, an optimum distribution of gate delays is proposed. Also, some critical aspects of selecting the delays are considered which may cause significant non-linearity with a dead zone and even oscillation of the phase frequency detector. The results of the analysis are verified by transistor level SPICE simulation.
Key words: phase frequency detector, charge pump, gate delay, transfer characteristic, dead zone.
Comparative
characteristics of 6H– and 4H–SiC surfaces in diffusion welding;
347–353
Oleg KOROLKOV and Toomas RANG
Abstract. The results of
experimental investigations of diffusion welded (bonded) large area Al/SiC
contacts are presented. The surface flatness of 4H–SiC structures with an
epitaxial layer is investigated. New data on crystal surface quality of
different producers are presented. The U–I characteristic of a large area
Al–4H–SiC Schottky structure based on Sterling SiC is briefly discussed.
Key words: SiC, diffusion welding technology, SiC wafer surface quality, Al–4H–SiC Schottky structure.
CHRONICLE
Leo Mõtus 60; 354–355
Raimund Ubar 60; 356–357
Contents of volume 7; 358–359