Software-based self-test generation for microprocessors with high-level decision diagrams; pp. 48–61Full article in PDF format
| doi: 10.3176/proc.2014.1.08
This paper presents a novel approach to automated behavioural level test program generation for microprocessors using the model of high-level decision diagrams (HLDD) for representing instruction sets. The methodology of using HLDDs for modelling of microprocessors, and a new HLDD-based fault model are developed. The procedures for automated test program generation are presented using a formal model of HLDDs. The feasibility and efficiency of the new methodology are demonstrated by carrying out experimental research on test generation for a 8-bit microprocessor. The results are promising, showing the advantages of the new method and demonstrating better quality of tests compared to previous results.
1. Niermann, T. M. and Patel, J. H. HITEC: A test generation package for sequential circuits. In Proc. European Confer. Design Automation, 1991, 214–218.
2. Bencivenga, R., Chakraborty, T. J., and Davidson, S. The architecture of the gentest sequential test generator. In Proc. Custom Integrated Circuits Conference, 1991, 17.1.1–17.1.4.
3. Eichelberger, E. B. and Williams, T. W. A logic design structure for LSI testability. In Proc. Design Automation Conference. New Orleans, 1977, 462–468.
4. Thatte, S. M. and Abraham, J. A. Test Generation for Microprocessors. IEEE T. Comput., 1980, C-29, 429–441.
5. Tupuri, R. S. and Abraham, J. A. A novel functional test generation method for processors using commercial ATPG. In Proc. Internat. Test Confer., 1997, 743–752.
6. Chen, L. and Dey, S. Software-based self-testing methodology for processor cores. IEEE T. Comput. Aid. D., 2001, 20, 369–380.
7. Chen, L., Ravit, S., Raghunathant, A., and Dey, S. A scalable software-based self-test methodology for programmable processors. In Proc. Design Automation Conference. Anaheim, Ca, 2003, 548–553.
8. Kranitis, N., Paschalis, A., Gizopoulos, D., and Xenoulis, G. Software-based self-testing of embedded processors. IEEE T. Comput., 2005, 54, 461–475.
9. Gurumurthy, R. S., Vasudevan, S., and Abraham, J. A. Automated mapping of pre-computed module-level test sequences to processor instructions. In Proc. Internat. Test Confer., 2005, 303–313.
10. Zhang, Y., Li, H., and Li, X. Automatic test program generation using executing-trace-based constraint extraction for embedded processors. IEEE T. VLSI Syst., 2013, 21, 1220–1233.
11. Kranitis, N., Merentitis, A., Theodorous, G., and Paschalis, A. Hybrid-SBST methodology for efficient testing of processor cores. IEEE Des. Test Comput., 2008, 25, 64–75.
12. Lu, T.-H., Chen, C.-H., and Lee, K.-J. Effective hybrid test program development for software-based self-testing of pipeline processor cores. IEEE T. VLSI Syst., 2011, 19, 516–520.
13. Wen, C. H.-P., Wang, Li-C., and Cheng, K.-T. Simulation-based functional test generation for embedded processors. IEEE T. Comput., 2006, 55, 1335–1343.
14. Ubar, R. Test synthesis with alternative graphs. IEEE Des. Test Comput., 1996, 48–59.
15. Karputkin, A., Ubar, R., Raik, J., and Tombak, M. Canonical representations of high level decision diagrams. Estonian J. Eng., 2010, 16, 39–55.
16. Navabi, Z. Analysis and Modeling of Digital Systems. McGraw-Hill, 1993.
17 Testing the Parwan processor. http://mesdat.ucsd.edu/~lichen/260c/parwan/ (accessed 6.03.2014).
18. Lee, C. Y. Representation of switching circuits by binary decision programs. AT &T Tech. J., 1959, 985–999.
19. Ubar, R., Raik, J., Jutman, A., Instenberg, M., and Wuttke, H.-D. Modeling microprocessor faults on high-level decision diagrams. In Internat. Confer. Dependable Systems and Networks. Anchorage, USA, 2008, c17–c22.
20. Zhang, Z., Li, H., and Li, X. Software-based self-testing of processors using expanded instructions. In Proc. 19th IEEE Asian Test Symposium
, 2010, 415–420.Back to Issue