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Estonian Journal of Engineering

System-level communication synthesis and dependability improvements for Network-on-Chip based systems; pp. 23–38

Full article in PDF format | doi: 10.3176/eng.2010.1.05

Mihkel Tagel, Peeter Ellervee, Gert Jervan

Technology scaling into subnanometer range will create process variations that have impact on the overall manufacturing yield and quality. Smaller feature sizes permit to pack more functionality into a single chip. Increasing variability, complexity and communication bandwidth requirements will make the System-on-Chip designer’s goal, to design a fault-free system, a very difficult task. Shift from traditional bus-based systems to networked systems solves several design problems but requires more focus on communication modelling. In this work we propose a system-level approach for communication modelling and synthesis. It makes possible to calculate precise communication delays that can be taken into account during application scheduling to avoid network congestions. We present a possible application of the proposed framework for scheduling fault-tolerant applications on non-reliable network.

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